NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 283

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

6—Intel
6.4
Table 145. Memory Decode Ranges from CPU Perspective (Sheet 1 of 2)
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Memory Map
Table 145
6300ESB ICH will decode. Cycles that arrive from the Hub Interface that are not
directed to any of the internal memory targets that decode directly from Hub Interface
will be driven out on PCI. The Intel
forwarded to LPC or claimed by the internal
I/O APIC or subtractive decode the cycle. When subtractive decode is enabled, the
subtractive decoded cycle may be forwarded to the LPC I/F or to the FWH.
PCI cycles generated by an external PCI master will be positively decoded unless it falls
in the PCI-PCI bridge forwarding range (those addresses are reserved for PCI peer-to-
peer traffic). When the cycle is not in the I/O APIC or FWH/LPC ranges, it will be
forwarded up the Hub Interface to the Host Controller. PCI masters cannot access the
memory ranges for functions that decode directly from Hub Interface.
NOTES:
1. These ranges are decoded directly from Hub Interface. The memory cycles will not be seen on
2. Software must not attempt locks to memory mapped I/O ranges for USB EHCI, High
FEC0 0000 - FEC0 0043
FEC1 0000 - FEC1 0043
0000 0000 - 000D FFFF
FFD0 0000 - FFD7 FFFF
FFD8 0000 - FFDF FFFF
000E 0000 - 000F FFFF
FFC0 0000 - FFC7 FFFF
FFC8 0000 - FFCF FFFF
FFB0 0000 - FFB7 FFFF
FFB8 0000 - FFBF FFFF
FF80 0000 - FF87 FFFF
FF88 0000 - FF8F FFFF
FF90 0000 - FF97 FFFF
FF98 0000 - FF9F FFFF
FFA0 0000 - FFA7 FFFF
FFE8 0000 - FFEF FFFF
FFA8 0000 - FFAF FFFF
FFF0 0000 - FFF7 FFFF
FFF8 0000 - FFFF FFFF
PCI.
Performance Event Timers, and IDE Expansion. When attempted, the lock is not honored,
which means potential deadlock conditions may occur.
FFE0 000 - FFE7 FFFF
0010 0000 - TOM
Memory Range
(Top of Memory)
shows, from the CPU perspective, the memory ranges that the Intel
Main Memory
6300ESB ICH
inside the
(D29:F5)
I/O APIC
I/O APIC
Target
Intel
FWH
FWH
FWH
FWH
FWH
FWH
FWH
FWH
FWH
®
®
6300ESB ICH may then claim the cycle for it to be
TOM registers in Host Controller
Bit 7 in FWH Decode Enable Register is set
Downstream memory writes to FEC0 0020 are
also decoded by D29:F5 APIC to support EOI.
D29:F5 APIC also supports FEC00000-FEC00043
range of message signaled interrupts from the
PCI-X interface (See Note 1)
Bit 0 in FWH Decode Enable Register
Bit 1 in FWH Decode Enable Register
Bit 2 in FWH Decode Enable Register is set
Bit 3 in FWH Decode Enable Register is set
Bit 4 in FWH Decode Enable Register is set
Bit 5 in FWH Decode Enable Register is set
Bit 6 in FWH Decode Enable Register is set.
Always enabled.
The top two 64K-byte blocks of this range may be
swapped, as described in
Block Update
Dependency/Comments
Scheme”.
Intel
®
Section 6.4.1, “Boot-
6300ESB I/O Controller Hub
®
283
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