NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 174

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Intel
DS
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6300ESB I/O Controller Hub
The following rules/steps apply when the system is in a G0 state and the policy is for
the Intel
10. When step 8 (reset attempt), is unsuccessful, then the Intel
11. This and the following rules/steps apply when the user intervention (power button
12. After step 1 (second timeout), when the user does a Power Button Override, the
13. After step 12 (power button override), when the user presses the power button
14. When step 13 (power button press) is successful in waking the system, the Intel
15. When step 13 (power button press) is unsuccessful in waking the system, the
16. After step 1 (second timeout), when a reset is attempted (using a button that
17. When step 16 (reset attempt) is successful, then the BIOS will be run. The Intel
18. When step 16 (reset attempt), is unsuccessful, then the Intel
1. Upon detecting the lockup the SECOND_TO_STS bit will be set. The Intel
2. After step 1, the Intel
3. Rules/steps 4-10 apply when no user intervention (resets, power button presses,
4. After step 3 (third timeout), when the user does a Power Button Override, the
5. After step 4 (power button override), when the user presses the power button
6. When step 5 (power button press) is successful in waking the system, the Intel
7. When step 5 (power button press) is unsuccessful in waking the system, the Intel
8. After step 3 (third timeout), when a reset is attempted (using a button that pulses
9. When step 8 (reset attempt) is successful, then the BIOS will be run. The Intel
6300ESB ICH will send a message with the Watchdog (WD) Event status bit set
(and any other bits that must also be set). This message will be sent as soon as the
lockup is detected, and will be sent with the next (incremented) sequence number.
until some external intervention occurs.
SMBus reset messages) occur after a third timeout of the watchdog timer. When
the intervention occurs before the third timeout, then jump to rule/step11.
system will go to an S5 state. The Intel
heartbeats at this point.
again, the system should wake to an S0 state and the processor should start
executing the BIOS.
6300ESB ICH will continue sending heartbeats until the BIOS clears the
SECOND_TO_STS bit.
6300ESB ICH will continue sending heartbeats. The Intel
attempt to reboot the system again until some external intervention occurs (reset,
power failure, etc.).
PWROK low or through the message on the SMBus slave I/F), the Intel
ICH will attempt to reset the system.
6300ESB ICH will continue sending heartbeats until the BIOS clears the
SECOND_TO_STS bit.
continue sending heartbeats. The Intel
the system again without external intervention.
press, reset, SMBus message, etc.) occur prior to the third timeout of the watchdog
timer.
system will go to an S5 state. The Intel
heartbeats at this point.
again, the system should wake to an S0 state and the processor should start
executing the BIOS.
6300ESB ICH will continue sending heartbeats until the BIOS clears the
SECOND_TO_STS bit.
Intel
not attempt to reboot the system again until some external intervention occurs
(reset, power failure, etc.).
pulses PWROK low or through the message on the SMBus slave I/F), the Intel
6300ESB ICH will attempt to reset the system.
6300ESB ICH will continue sending heartbeats until the BIOS clears the
SECOND_TO_STS bit.
continue sending heartbeats. The Intel
the system again without external intervention.
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6300ESB ICH will continue sending heartbeats. The Intel
6300ESB ICH to not reboot the system after a hardware lockup:
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6300ESB ICH will send a message every heartbeat period
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6300ESB ICH will not attempt to reboot
6300ESB ICH will not attempt to reboot
6300ESB ICH will continue sending
6300ESB ICH will continue sending
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6300ESB ICH will not
Order Number: 300641-004US
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6300ESB ICH will
Intel
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6300ESB ICH will
6300ESB ICH will
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6300ESB ICH—5
November 2007
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6300ESB
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