NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 321

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
8.1.14
Table 194. Offset 58h - 5Bh: GPIO_BASE—GPIO Base Address (LPC I/F—D31:F0)
8.1.15
Table 195. Offset 5Ch: GPIO_CNTL—GPIO Control (LPC I/F—D31:F0)
November 2007
Order Number: 300641-004US
31:1
15:6
Bits
Bits
Default Value:
Default Value:
5:1
7:5
3:0
6
0
4
Lockable:
Lockable:
®
Note: Sets base address for GPIO registers. May be mapped anywhere in the 64K I/O space
Device:
Device:
Offset:
Offset:
GPIO_EN: GPIO Enable
6300ESB ICH
Resource Indicator
Base Address
Offset 58h - 5Bh: GPIO_BASE—GPIO Base Address
(LPC I/F—D31:F0)
on 128-byte boundaries.
Offset 5Ch: GPIO_CNTL—GPIO Control (LPC I/F—
D31:F0)
Reserved
Reserved
Reserved
Reserved
31
58h-5Bh
00000001h
No
Name
31
5Ch
00h
No
Name
Reserved.
Provides the 64 bytes of I/O space for GPIO.
Reserved.
Tied to 1 to indicate I/O space.
Reserved.
This bit enables/disables decode of the I/O range pointed to
by the GPIO base register and enables/disables the GPIO
function.
0 = Disable.
1 = Enable.
Reserved.
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0
Read/Write
32-bit
Core
0
Read/Write
8-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
Access
R/W
R/W
RO
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