NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 166

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.11.11.3VRMPWRGD Signal
Intel
DS
166
®
6300ESB I/O Controller Hub
The VRMPWRGD signal is not implemented in the Intel
need to be pulled up to Vcc in order to disable internal legacy logic. If not pulled up,
this logic may come up in an unknown state.
1. Traditional designs have a reset button logically ANDs with the PWROK signal from
2. PWROK and RSMRST# are sampled using the RTC clock. Therefore, low times that
the power supply and the processor’s voltage regulator module. When this is done
with the Intel
ICH treats this internally as though the RSMRST# signal had gone active. However,
it is not treated as a full power failure. When PWROK goes inactive and then active
(but RSMRST# stays high), then the Intel
the state of the AFTERG3 bit). When the RSMRST# signal also goes low before
PWROK goes high, then this is a full power failure and the reboot policy is
controlled by the AFTERG3 bit.
are less than one RTC clock period may not be detected by the Intel
ICH.
®
6300ESB ICH, the PWROK_FLR bit will be set. The Intel
®
6300ESB ICH will reboot (regardless of
®
6300ESB ICH. VRMPWRGD
Order Number: 300641-004US
Intel
®
®
6300ESB ICH—5
6300ESB
November 2007
®
6300ESB