NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 604

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

14.2.10 CAS—Codec Access Semaphore Register
Intel
DS
604
Bits
Bits
Default Value:
Default Value:
4:3
7:1
I/O Address:
7
6
5
2
1
0
I/O Address:
0
®
Table 526. GLOB_STA—Global Status Register (Sheet 3 of 3)
Table 527. CAS—Codec Access Semaphore Register
6300ESB I/O Controller Hub
Lockable:
Lockable:
Note: Reads across dWord boundaries are not supported.
PCM In Interrupt (PIINT)
Device:
Device:
Mic In Interrupt (MINT)
Modem Out Interrupt
Modem In Interrupt
GPI Status Change
PCM Out Interrupt
Semaphore (CAS)
Interrupt (GSCI)
Codec Access
Reserved
Reserved
(MOINT)
(POINT)
(MIINT)
29
MBAR + 40h
00300000h
No
Name
29
NABMBAR + 44h
00h
No
Name
This bit indicates that one of the Mic in channel interrupts
status bits has been set. When the specific status bit is
cleared, this bit will be cleared.
This bit indicates that one of the PCM out channel interrupts
status bits has been set. When the specific status bit is
cleared, this bit will be cleared.
This bit indicates that one of the PCM in channel interrupts
status bits has been set. When the specific status bit is
cleared, this bit will be cleared.
Reserved.
This bit indicates that one of the modem out channel
interrupts status bits has been set. When the specific status
bit is cleared, this bit will be cleared.
This bit indicates that one of the modem in channel interrupts
status bits has been set. When the specific status bit is
cleared, this bit will be cleared.
This bit reflects the state of bit ’0’ in slot 12, and is set
whenever bit ’0’ of slot 12 is set. This indicates that one of
the GPIs changed state, and that the new values are available
in slot 12. The bit is cleared by software writing a ‘1’ to this
bit location.
This bit is not affected by D3
Reserved.
This bit is read by software to check whether a codec access
is currently in progress.
0 = No access in progress.
1 = The act of reading this register sets this bit to 1. The
driver that read this bit may then perform an I/O access.
Once the access is completed, hardware automatically
clears this bit.
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
HOT
Size:
Size:
to D0 Reset.
5
Read-Only, Read/Write, Read/Write Clear
32-bit
Core
5
Read/Write
8-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—14
November 2007
(special)
Access
Access
R/WC
R/W
RO
RO
RO
RO
RO
RO