NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 715

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

19—Intel
Table 644. FIFO Control Register (FCR) (Sheet 2 of 2)
19.5.1.3.6 Line Control Register (LCR)
November 2007
Order Number: 300641-004US
®
6300ESB ICH
In the Line Control Register (LCR), the system programmer specifies the format of the
asynchronous data communications exchange. The serial data format consists of a start
bit (logic 0), five to eight data bits, an optional parity bit, and one or two stop bits
(logic 1). The LCR has bits for accessing the Divisor Latch and causing a break
condition. The programmer may also read the contents of the Line Control Register. The
read capability simplifies system programming and eliminates the need for separate
storage in system memory.
FIFO Control Register
FCR
write-only
Number
5:3
Bit
2
1
0
Bit Mnemonic
RESETTF
RESETRF
TRFIFOE
–
Address:
Reset State:
Access:
Reserved
Reset Transmitter FIFO: When RESETTF is set to 1, the
transmitter FIFO counter logic is set to 0, effectively clearing all
the bytes in the FIFO. The TDRQ bit in LSR are set and IIR shows
a transmitter requests data interrupt if the TIE bit in the IER
register is set. The transmitter shift register is not cleared; it
completes the current transmission. After the FIFO is cleared,
RESETTF is automatically reset to 0.
0 = Writing ’0’ has no effect.
1 = The transmitter FIFO is cleared (FIFO counter set to 0). After
clearing, bit is automatically reset to 0.
Reset Receiver FIFO: When RESETRF is set to 1, the receiver
FIFO counter is reset to 0, effectively clearing all the bytes in the
FIFO. The DR bit in LSR is reset to 0. All the error bits in the FIFO
and the FIFOE bit in LSR are cleared. Any error bits, OE, PE, FE
or BI, that had been set in LSR are still set. The receiver shift
register is not cleared. If IIR had been set to Received Data
Available, it is cleared. After the FIFO is cleared, RESETRF is
automatically reset to 0.
0 = Writing ’0’ has no effect.
1 = The receiver FIFO is cleared (FIFO counter set to 0). After
clearing, bit is automatically reset to 0.
Transmit and Receive FIFO Enable: TRFIFOE enables/disables
the transmitter and receiver FIFOs. When TRFIFOE = 1, both
FIFOs are enabled (FIFO Mode). When TRFIFOE = 0, the FIFOs
are both disabled (non-FIFO Mode). Writing a ’0’ to this bit clears
all bytes in both FIFOs. When changing from FIFO mode to non-
FIFO mode and vice versa, data is automatically cleared from the
FIFOs. This bit must be 1 when other bits in this register are
written or the other bits are not programmed.
0 = FIFOs are disabled.
1 = FIFOs are enabled.
Base + 02H
00H
8-bit
Function
Intel
®
6300ESB I/O Controller Hub
715
DS