NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 146

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.11.2
Table 62.
Intel
DS
146
®
6300ESB I/O Controller Hub
Intel
Rules
Table 62
state names generally match the corresponding ACPI states.
General Power States for Systems Using Intel
Substates
G0/S0/C0
G0/S0/C1
G0/S0/C2
State/
G1/S1
G1/S3
G1/S4
G2/S5
G3
®
shows the power states defined for Intel
6300ESB ICH Power States and Transition
Full On: Processor operating. Individual devices may be shut down to save power.
The different processor operating levels are defined by Cx states, as shown in
Table
signal to reduce power consumption. The throttling may be initiated by software or
by the THRM# input signal.
Auto-Halt: Processor has executed a AutoHalt instruction and is not executing
code. The processor snoops the bus and maintains cache coherency.
Stop-Grant: The STPCLK# signal goes active to the processor. The processor
performs a Stop-Grant cycle, halts its instruction stream, and remains in that state
until the STPCLK# signal goes inactive. In the Stop-Grant (desktop) state, the
processor snoops the bus and maintains cache coherency.
NOTE: This state is not supported for IA64 processors. They should instead use
Stop-Grant: Similar to G0/S0/C2 state. The Intel
option to assert the CPUSLP# signal to further reduce processor power
consumption.
NOTE: The behavior for this state is slightly different when supporting IA64
Suspend-To-RAM (STR): The system context is maintained in system DRAM, but
power is shut off to non-critical circuits. Memory is retained, and refreshes
continue. All clocks stop except RTC clock.
Suspend-To-Disk (STD): The context of the system is maintained on the disk. All
power is then shut off to the system except for the logic required to resume.
Soft Off (SOFF): System context is not maintained. All power is shut off except
for the logic required to restart.
Mechanical OFF (MOFF): System context not maintained. All power is shut off
except for the RTC. No “Wake” events are possible, because the system does not
have any power. This state occurs when the user removes the batteries, turns off a
mechanical switch, or when the system power supply is at a level that is
insufficient to power the “waking” logic. When system power returns, transition will
depends on the state just prior to the entry to G3 and the AFTERG3 bit in the
GEN_PMCON3 register (D31:F0, offset A4). Refer to
63. Within the C0 state, the Intel
C1.
processors.
Legacy Name / Description
A full boot is required when waking.
®
®
6300ESB ICH may throttle the STPCLK#
6300ESB ICH-based platforms. The
®
®
6300ESB ICH also has the
6300ESB ICH
Table 71
Order Number: 300641-004US
Intel
for more details.
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6300ESB ICH—5
November 2007