NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 43

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Contents—Intel
November 2007
Order Number: 300641-004US
537 Memory Mapped Registers....................................................................................... 618
538 Offset 00h: VID—Vendor Identification Register ......................................................... 618
539 Offset 02h: DID—Device Identification Register.......................................................... 619
540 Offset 04 - 05h: COM—Command Register ................................................................ 619
541 Offset 06h - 07h: DS—Device Status Register ............................................................ 620
542 Offset 08h: RID—Revision Identification Register........................................................ 621
543 Offset 09h: PI—Programming Interface Register ........................................................ 622
544 Offset 0Ah: SCC—Sub Class Code Register ................................................................ 622
545 Offset 0Bh: BCC—Base Code Class Register ............................................................... 622
546 Offset 0Eh: HEDT—Header Type Register .................................................................. 623
547 Offset 10h: BAR—Base Address Register ................................................................... 623
548 Offset 2Dh - 2Ch: SVID—Subsystem Vendor ID ......................................................... 624
549 Offset 2Eh - 2Fh: SID—Subsystem ID ....................................................................... 624
550 Offset 60 - 61h: WDT Configuration Register ............................................................. 625
551 Offset 68h: WDT Lock Register ................................................................................ 626
552 Offset F8 - FBh: Manufacturer’s ID ........................................................................... 627
553 Offset Base + 00h: Preload Value 1 Register.............................................................. 627
554 Offset Base + 04h: Preload Value 2 Register.............................................................. 628
555 Offset Base + 08h: General Interrupt Status Register ................................................. 628
556 Offset Base + 0Ch: Reload Register .......................................................................... 629
557 APIC1 Configuration Map (D29:F5) ........................................................................... 631
558 Offset 00 - 03h: VID_DID—Vendor/ID Register (APIC1—D29:F5) ................................. 632
559 Offset 04 - 05h: APIC1CMD—APIC1 COMMAND Register (APIC1—D29:F5) ..................... 632
560 Offset 06 - 07h: APIC1STA—APIC1 Device Status (APIC1—D29:F5) .............................. 633
561 Offset 08h: RID—Revision ID Register (APIC1—D29:F5).............................................. 634
562 Offset 09 - 0Bh: CC—Class Code Register (APIC1—D29:F5) ......................................... 634
563 Offset 0C - 0Fh: HEADTYP—Header Type Register (APIC1—D29:F5).............................. 635
564 Offset 2C - 2Fh: SS—APIC1 Subsystem Identifiers (APIC1—D29:F5) ............................. 635
565 Offset 34h: CAP_PTR—APIC1 Capabilities Pointer (APIC1—D29:F5)............................... 636
566 Offset 3Ch: ILINE—Interrupt Line (APIC1—D29:F5) .................................................... 636
567 Offset 3Dh: IPIN—Interrupt Pin (APIC1—D29:F5) ....................................................... 636
568 Offset 40 - 41h: ABAR—APIC1 Alternate Base Address Register (APIC1—D29:F5) ........... 637
569 Offset 44 - 47h: MBAR—APIC1 Memory Base Register (APIC1—D29:F5) ........................ 638
570 Offset 50 - 51h: XID—PCI-X Identifiers Register (APIC1—D29:F5) ................................ 639
571 Offset 52h: XSR—PCI-X Status Register (APIC1—D29:F5) ........................................... 639
572 APIC1 Direct Registers ............................................................................................ 640
573 APIC Indirect Registers ........................................................................................... 640
574 IND—Index Register ............................................................................................... 641
575 DAT—Data Register ................................................................................................ 641
576 IRQPA—IRQ Pin Assertion Register ........................................................................... 642
577 EOIR—EOI Register ................................................................................................ 642
578 Offset 00h: ID—Identification Register ...................................................................... 643
579 Offset 01h: VER—Version Register............................................................................ 643
580 Offset 03h: BOOT_CONFIG—Boot Configuration Register ............................................. 644
581 Redirection Table ................................................................................................... 644
582 Configuration Addressing ........................................................................................ 650
583 Comparison of Rules vs. A PCI – PCI Bridge ............................................................... 652
584 Configuration Space Register Summary..................................................................... 653
585 Offset 00: ID—Identifiers ........................................................................................ 654
586 Offset 04: CMD—Command ..................................................................................... 655
587 Offset 06: PSTS—Primary Status .............................................................................. 657
588 Offset 08: RID—Revision ID .................................................................................... 658
589 Offset 09: CC—Class Code ...................................................................................... 659
590 Offset 0C: CLS—Cache Line Size .............................................................................. 659
591 Offset 0D: PLT—Primary Latency Timer ..................................................................... 660
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6300ESB ICH
Intel
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6300ESB I/O Controller Hub
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