NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 4

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Intel
DS
4
®
6300ESB I/O Controller Hub
•
•
•
•
•
USB
AC'97 Link for Audio and Telephony
CODECs
Interrupt Controller
New: Multimedia Timers based on 82C54
New: Watchdog Timer
— Includes one EHCI USB2 host
— Two UHCI Host Controllers for a total of
— New: supports a USB 2.0 High-speed
— Supports wake-up from sleeping states
— Supports legacy Keyboard/Mouse
— New: Third AC_SDATA_IN Line for three
— AC’97 2.2 compliant
— New: Independent bus master logic for
— Separate independent PCI functions for
— Support for up four to six channels of
— Support for 20-bit sample
— Support for ACPI device states - D0 and
— Supports up to 12 PCI interrupt pins;
— Two cascaded 82C59 with 15 interrupts
— Supports PCI scheme for delivering
— Integrated I/O APIC capability with 24
— Supports Serial Interrupt Protocol
— Supports Front-Side Message Interrupt
— Includes three timer comparators
— System timer, Refresh request, Speaker
— One-shot and periodic interrupts
— Two-Stage Watchdog with independent
— First stage generates an INT or SMI
— Second stage drives external pin active
— Configuration option for write-once
— Configurable granularity from 1µs to 10
controllers, a total of four ports (shared
with the UHCI ports)
four ports (shared with EHCI ports)
Debug Port
S1-S4
software with USB-based keyboard and
mouse
codec support
8 channels (PCM In/Out, Mic 1 Input,
Mic 2 Input, Modem In/Out, S/PDIF
Out)
Audio and Modem
PCM audio output (full AC3 decode)
D3
four are not shared
interrupts as write cycles (MSI)
interrupts
Delivery
tone output
supported
count values for each stage
until cleared by a system reset or power
cycle
enabling (count values can still change)
min
•
•
•
•
•
•
•
SMBus
New: Integrated 16550 compatible UARTs
New: Port 60/64 Emulation
GPIO
1.5 V operation with 3.3 V I/O. 5 V
tolerance on many buffers, including IDE.
Package 37.5 x 37.5 mm 689 BGA
Process P859.6
— Flexible SMBus/SMLink architecture to
— Supports SMBus 2.0 Specification
— Host interface allows CPU to
— Slave interface allows an external
— Compatible with most 2-wire
— Enable/disable per UARTs
— Serial interrupts
— Can disable when external SIO used
— Programmable interrupt generation on
— Positive decode to Port 60/64 emulation
— Four GPOs capable of directly driving
— Two GPOs maintain state during and
optimize for ASF and eliminate board
requirements of SMBus 2.0 compliance
communicate via SMBus
Microcontroller to access system
resources
components that are also I
compatible
writes
registers
LEDs
after reset
Order Number: 300641-004US
Intel
®
6300ESB ICH—
2
November 2007
C