NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 426

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8.10.2
Table 314. Offset GPIOBASE + 00h: GPIO_USE_SEL—GPIO Use Select Register
8.10.3
Table 315. Offset GPIOBASE + 04h: GP_IO_SEL—GPIO Input/Output Select
Intel
DS
426
9, 26
21:1
31:2
28:2
25:2
Bits
Bits
Default Value:
Default Value:
23,
11,
7:0
23
6,
7
4
®
6300ESB I/O Controller Hub
Lockable:
Lockable:
Device:
GPIO_USE_SEL[0:7, 11,
Device:
Offset:
Offset:
GPIO[n]_SEL
16:21, 23]
Offset GPIOBASE + 00h: GPIO_USE_SEL—GPIO
Use Select Register
Offset GPIOBASE + 04h: GP_IO_SEL—GPIO
Input/Output Select Register
Register
Reserved
31
GPIOBASE + 00h
1B003100h
Yes
Name
31
GPIOBASE +04h
0000FFFFh
No
Name
Enables GPIO[n] (where n is the bit number) to be used as a
GPIO, rather than for the native function.
1 = Signal used as GPIO (or unmuxed). 0 = Signal used as
native function.
Notes:
Reserved.
0 = Output. The corresponding GPIO signal is an output.
1 = Input. The corresponding GPIO signal is an input.
Always 0. The GPIOs are fixed as outputs.
1. The following bits are not implemented because there is no
2. The following bits are always 1 because they are
3. When GPIO[n] does not exist, the bit in this register will
4. After a full reset (RSMRST#) all multiplexed signals in the
corresponding GPIO: 9:10, 14:15, 22,
26 and 29:31.
unmuxed: 8, 12:13, 24, 25, 27:28.
always read as 0 and writes will have no effect.
resume and core wells are configured as their native
function rather than as a GPIO. After just a PXPCIRST#,
the GPIO in the core well are configured as their native
function.
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0
Read/Write
32-bit
Core for 0:7 and 16:21, 23
Resume for 8:15 and 24:31
0
Read-Only
32-bit
Resume
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
Access
R/W