NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 135

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
Table 54.
Table 55.
5.8
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Interrupt Message Address Format (Sheet 2 of 2)
Interrupt Message Data Format
Serial Interrupt (D31:F0)
The Intel
used to report interrupt requests. The signal used to transmit this information is shared
between the host, the Intel
interrupts. The signal line, SERIRQ, is synchronous to PCI clock, and follows the
sustained tri-state protocol that is used by all PCI signals. This means that when a
device has driven SERIRQ low, it will first drive it high synchronous to PCI clock and
release it the following PCI clock. The serial IRQ protocol defines this sustained tri-state
signaling in the following fashion:
•
•
31:16
13:12
10:8
1:0
7:0
Bit
Bit
15
14
11
3
2
S - Sample Phase. Signal driven low
R - Recovery Phase. Signal driven high
Will always be 0000h.
Will always be 00
Redirection Hint: This bit is used by the processor host bridge to allow the interrupt
message to be redirected.
0 = The message will be delivered to the agent (processor) listed in bits 19:12.
1 = The message will be delivered to an agent with a lower interrupt priority. This may
be derived from bits 10:8 in the Data Field (see below).
The Redirection Hint bit will be a 1 when bits 10:8 in the delivery mode field associated
with corresponding interrupt are encoded as 001 (Lowest Priority). Otherwise, the
Redirection Hint bit will be 0.
Destination Mode: This bit is used only the Redirection Hint bit is set to 1. When the
Redirection Hint bit and the Destination Mode bit are both set to 1, then the logical
destination mode is used, and the redirection is limited only to those processors that
are part of the logical group as based on the logical ID.
Will always be 00.
Trigger Mode: 1 = Level, 0 = Edge. Same as the corresponding bit in the I/O
Redirection Table for that interrupt.
Delivery Status: 1 = Assert, 0 = Deassert.
When using edge-triggered interrupts, this bit will always be 1, since only the assertion
is sent.
When using level-triggered interrupts, this bit indicates the state of the interrupt input.
Destination Mode: 1 = Logical. 0 = Physical. Same as the corresponding bit in the I/
O Redirection Table for that interrupt.
Delivery Mode: This is the same as the corresponding bits in the I/O Redirection Table
for that interrupt.
000 = Fixed 100 = NMI
001 = Lowest Priority 101 = INIT
010 = SMI/PMI 110 = Reserved
011 = Reserved 111 = ExtINT
Vector: This is the same as the corresponding bits in the I/O Redirection Table for that
interrupt.
®
6300ESB ICH supports a serial IRQ scheme. This allows a single signal to be
®
6300ESB ICH, and all peripherals that support serial
Description
Description
Intel
®
6300ESB I/O Controller Hub
135
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