NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 631

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

17—Intel
APIC1 Configuration Registers
(D29:F5)
17.1
Table 557. APIC1 Configuration Map (D29:F5) (Sheet 1 of 2)
.
November 2007
Order Number: 300641-004US
Note: Registers that are not shown should be treated as Reserved. See
®
6300ESB ICH
APIC1’s direct registers are assigned with base address FEC1xxxxH. To support legacy
device/driver on external PCI bus used with the Intel ICHx, APIC1 has an alternate
base address FEC0xxxxH. This means external PCI devices may write to IRQ pin
assertion register (either FEC0_0020H or FEC1_0020H) to generate interrupt from
APIC1. Devices on the primary PCI bus can write to IRQ Pin Assertion Register
FEC0_0020H to generate an APIC0 interrupt. Devices/drivers on the PCI-X segment
have write access only on the APIC1 IRQ Pin Assertion Register. Devices/drivers on the
PCI segment can access only APIC0 registers.
Since the Intel
MCH will translate EOI special cycle to a memory write cycle to EOI register at address
FEC0_0040H and pass it to the Intel
passed to both APIC0 and APIC1 internally.
From CPU/MCH point of view, it should always use address FEC0xxxxH to access APIC0
registers and address FEC1xxxxH to access APIC1 registers. APIC1 will not respond to
CPU/MCU’s access to address FEC0xxxxH other than the EOI cycle stated above.
APIC1 also includes an XAPIC_EN config bit. This bit must be set to enable the I/O (x)
APIC extension to the I/O APIC. For APIC1, this extension is always enabled.
APIC1 Configuration Registers (D29:F5)
Map” on page 277
NOTES:
1. Refer to the Intel
00-03h
04-05h
06-07h
09-0Bh
0C-0Fh
40-41h
Offset
2C-2F
value of the Revision ID Register.
3Ch
3Dh
08h
34h
®
Mnemonic
APIC1CMD
APIC1STA
HEADTYP
VID_DID
6300ESB ICH does not implement Hub Interface EOI special cycle,
ILINE
ABAR
IPIN
CAP
RID
CC
SS
®
for details.
6300ESB I/O Controller Hub Specification Update for the most up-to-date
Vendor ID/Device ID
APIC1 Command Register
APIC1 Device Status Register
Revision ID
Class Code
Header Type
Subsystem Identifiers
Capabilities Pointer
Interrupt Line
Interrupt Pin
Alternate Base Address Register
®
Register Name
6300ESB ICH. This memory write cycle will be
Intel
25ACH/8086h
®
00000000h
00000000h
See
6300ESB I/O Controller Hub
080020h
“PCI Configuration
Default
0000h
0010h
8000h
50h
00h
00h
Note 1
17
Type
RWO
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
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