NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 619

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

16—Intel
16.4.4
Table 539. Offset 02h: DID—Device Identification Register
16.4.5
Table 540. Offset 04 - 05h: COM—Command Register
November 2007
Order Number: 300641-004US
15:0
15:1
Bits
Bits
Default Value:
Default Value:
0
9
8
7
6
5
4
3
2
1
0
Lockable:
Lockable:
BME - Bus Master Enable Reserved as ‘0’.
Device:
Device:
IOSE - I/O Space Enable Reserved as ‘0’.
®
Offset:
Offset:
Parity Error Response
Memory Write Enable
MSE - Memory Space
6300ESB ICH
SCE - Special Cycle
VGA Palette Snoop
Wait Cycle Control
Fast Back-to-Back
PMWE - Postable
SERR# Enable
Enable (FBE)
Offset 02h: DID—Device Identification Register
Device ID
Offset 04 - 05h: COM—Command Register
Reserved
Enable
Enable
29
02h
25ABh
No
Name
29
04 - 05h
0000h
No
Name
Reserved.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
This bit controls access to the WDT’s Memory Mapped
registers. If this bit is set, accesses to the WDT’s Memory
Mapped registers are enabled. The Base Address register for
WDT should be programmed before this bit is set.
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
4
Read-Only
16-bit
Core
4
Read-Only
16-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
Access
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
NA
619
DS