NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 661
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NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
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Compliant
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18—Intel
18.6.1.10Offset 18: BNUM—Bus Numbers
18.6.1.11Offset 1B: SLT—Secondary Latency Timer
November 2007
Order Number: 300641-004US
23:1
15:0
07:0
07:0
02:0
Bits
Bits
6
8
0
3
0
Table 593. Offset 18: BNUM—Bus Numbers
Table 594. Offset 1B: SLT—Secondary Latency Timer
Note: This contains the primary, secondary, and maximum subordinate bus number registers.
Note: This timer controls the amount of time that the Intel
®
Subordinat
Timer (TV)
Secondary
Secondary
Device
Device
Offset
Offset
Reserved
Number
Number
Primary
Number
Latency
(SBBN)
(SCBN)
6300ESB ICH
Name
Name
(PBN)
e Bus
Bus
Bus
data on its secondary interface. The counter starts counting down from the assertion of
PXFRAME#. When the grant is removed, the expiration of this counter results in the
deassertion of PXFRAME#. When the grant has not been removed, the Intel
ICH may continue ownership of the bus. The secondary latency timer's default value
should be 64 in PCI-X mode (Section 8.6.1 of the PCI-X 1.0 Specification).
28
18
28
1B
Indicates the highest PCI bus number below this bridge. Any
type one configuration cycle on the Hub Interface whose bus
number is greater than the secondary bus number and less
than or equal to the subordinate bus number is run as a type
one configuration cycle on the PCI bus.
Indicates the bus number of PCI to which the secondary
interface is connected. Any type one configuration cycle
matching this bus number is translated to a type 0
configuration cycle and run on the PCI bus.
Indicates the bus number of the Hub Interface. Any type 1
configuration cycle with a bus number less than this number
is not accepted by this portion of the Intel
(i.e., it still may match the other bridge).
A five-bit value that indicates the number of PCI clocks, in 8-
clock increments, that the Intel
master of the PCI bus when another master is requesting use
of the PCI bus.
Reserved.
Description
Description
®
6300ESB ICH remains as a
Attribute:
Attribute:
Function
Function
®
Size:
Size:
6300ESB ICH
0
Read/Write
24-bit
0
Read/Write
8-bit
®
6300ESB ICH continues to burst
Intel
®
Reset
Value
Reset
Value
6300ESB I/O Controller Hub
00h
00h
00h
00h
000
®
Access
Access
6300ESB
R/W
R/W
R/W
R/W
RO
661
DS
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