NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 295

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

7—Intel
7.1.15
Table 161. Offset 1Dh: IOLIM—I/O Limit Register (HUB-PCI—D30:F0)
7.1.16
Table 162. Offset 1E - 1Fh: SECSTS—Secondary Status Register (HUB-PCI—
November 2007
Order Number: 300641-004US
10:9
Bits
Bits
Default Value:
Default Value:
7:4
3:0
15
14
13
12
11
®
Note: For the writable bits in this register, writing a 1 will clear the bit. Writing a 0 to the bit
Device:
Device:
DEVSEL# Timing Status
Offset:
Offset:
6300ESB ICH
Received System Error
Received Master Abort
I/O Address Limit bits
Received Target Abort
Signaled Target Abort
Detected Parity Error
I/O Addressing
Offset 1Dh: IOLIM—I/O Limit Register (HUB-PCI—
D30:F0)
Capability
Offset 1E - 1Fh: SECSTS—Secondary Status
Register (HUB-PCI—D30:F0)
will have no effect.
D30:F0)
[15:12]
30
1Dh
00h
Name
30
1E-1Fh
0280h
Name
(RMA)
(DPE)
(SSE)
(RTA)
(STA)
I/O Base bits corresponding to address lines 15:12 for
4 Kbyte alignment. Bits 11:0 are assumed to be padded to
FFFh.
This is hardwired to 0h, indicating that the Hub Interface-to-
PCI bridge does not support 32-bit I/O addressing. This
means that the I/O base and limit upper address registers
must be read only.
0 = This bit is cleared by software writing a 1.
1 = The Intel
0 = Software clears this bit by writing a’1’ to the bit position.
1 = SERR# assertion is received on PCI.
0 = Software clears this bit by writing a’1’ to the bit position.
1 = Hub Interface to PCI cycle was master-aborted on PCI.
0 = Software clears this bit by writing a’1’ to the bit position.
1 = Hub Interface to PCI cycle was target-aborted on PCI. For
Intel
01h = Medium timing.
PCI bus.
“completion required” cycles from the Hub Interface, this
event should also set the Signaled Target Abort in the
Primary Status Register in this device, and the Intel
6300ESB ICH must send the “target abort” status back to
the Hub Interface.
®
6300ESB ICH does not generate target aborts.
®
6300ESB ICH detected a parity error on the
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0
Read/Write
8-bit
0
Read/Write
16-bit
Intel
®
6300ESB I/O Controller Hub
®
Access
Access
R/WC
R/WC
R/WC
R/WC
R/W
RO
RO
RO
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