NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 183

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.14.3.2 Line Buffer
5.14.3.3 Bus Master IDE Timings
5.14.3.4 Interrupts
November 2007
Order Number: 300641-004US
Caution:In this mode, the Intel
®
6300ESB ICH
A single line buffer exists for the Intel
buffer is not shared with any other function. The buffer is maintained in either the read
state or the write state. Memory writes are typically 4-DWORD bursts and invalid
DWORDs have C/BE[3:0]#=0Fh. The line buffer allows burst data transfers to proceed
at peak transfer rates.
The Bus Master IDE Active bit in Bus Master IDE Status register is reset automatically
when the controller has transferred all data associated with a Descriptor Table (as
determined by EOT bit in last PRD). The IDE Interrupt Status bit is set when the IDE
device generates an interrupt. These events may occur prior to line buffer emptying for
memory writes. When either of these conditions exist, all PCI Master non-Memory read
accesses to the Intel
been transferred to memory.
The timing modes used for Bus Master IDE transfers are identical to those for PIO
transfers. The DMA Timing Enable Only bits in IDE Timing register may be used to
program fast timing mode for DMA transactions only. This is useful for IDE devices
whose DMA transfer timings are faster that its PIO transfer timings. The IDE device
DMA request signal is sampled on the same PCI clock that DIOR# or DIOW# is
deasserted. When inactive, the DMA Acknowledge signal is deasserted on the next PCI
clock and no more transfers take place until DMA request is asserted again.
Legacy Mode:
The Intel
the secondary interrupt. This connection is done from the ISA pin, before any mask
registers. This implies the following:
associated with this function. That is only used in native mode.
Native Mode:
In this case both the Primary and Secondary channels share an interrupt. It will be
internally connected to PIRQ[C]# (IRQ18 in APIC mode). The interrupt will be active-
low and shared.
Behavioral notes in native mode
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Bus Master IDE is operating under an interrupt based driver. Therefore, it will not
operate under environments where the IDE device drives an interrupt but the
interrupt is masked in the system.
Bus Master IDE devices are connected directly off of the Intel
interrupts cannot be communicated through PCI devices or the serial stream.
The IRQ14 and IRQ15 pins do not affect the internal IRQ14 and IRQ15 inputs to the
interrupt controllers. The IDE logic forces these signals inactive in such a way that
the Serial IRQ source may be used.
The IRQ14 and IRQ15 inputs (not external IRQ[14:15] pins) to the interrupt
controller may come from other sources (Serial IRQ, PIRQx).
The IRQ14 and IRQ15 pins are inverted from active-high to the active-low PIRQ.
®
6300ESB ICH is connected to IRQ14 for the primary interrupt and IRQ15 for
®
6300ESB ICH are retried until all data in the line buffers has
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6300ESB ICH will not drive the PCI Interrupt
®
6300ESB ICH Bus master IDE interface. This
Intel
®
6300ESB I/O Controller Hub
®
6300ESB ICH. IDE
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