NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 405

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
Table 291. GPE0_EN—General Purpose Event 0 Enables Register (Sheet 2 of 2)
8.8.3.9
Table 292. SMI_EN—SMI Control and Enable Register (Sheet 1 of 3)
November 2007
Order Number: 300641-004US
31:1
16:1
Bits
Bits
Default Value:
Default Value:
18
17
I/O Address:
I/O Address:
4
3
2
1
0
9
5
Lockable:
Lockable:
®
Note: Usage: ACPI or Legacy
Device:
Device:
6300ESB ICH
LEGACY_USB2_EN
INTEL_USB2_EN
THRM#_POL
THRM_EN
SMI_EN—SMI Control and Enable Register
USB2_EN
USB1_EN
Reserved
Reserved
Reserved
31
PMBASE + 2Ch
(ACPI GPE0_BLK + 4)
00000000h
No
Name
31
PMBASE + 30h
00000000h
No
Name
0 = Disable.
1 = Enable the setting of the USB2_STS bit to generate a
0 = Disable.
1 = Enable the setting of the USB1_STS bit to generate a
This bit controls the polarity of the THRM# pin needed to set
the THRM_STS bit.
0 = Low value on the THRM# signal will set the THRM_STS
1 = HIGH value on the THRM# signal will set the THRM_STS
Reserved.
0 = Disable.
1 = Active assertion of the THRM# signal (as defined by the
Reserved.
Enables Intel-Specific USB EHCI SMI logic to cause SMI#.
Enables legacy USB EHCI logic to cause SMI#.
Reserved.
wake event. The USB2_STS bit is set anytime USB UHCI
Controller #2 signals a wake event. Break events are
handled through the USB interrupt.
wake event. The USB1_STS bit is set anytime USB UHCI
Controller #1 signals a wake event. Break events are
handled through the USB interrupt.
bit.
bit.
THRM_POL bit) will set the THRM_STS bit and generate a
power management event (SCI or SMI).
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0
Read/Write
32-bit
Bits 0-7, 12, 16-31 Resume,
Bits 8-11, 13 RTC
0
Read/Write
32-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
Access
R/W
R/W
R/W
R/W
405
DS