NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 101

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.2.1.7
Figure 9.
Figure 10. Abort Mechanism
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Upon recognizing the SYNC field indicating an error, the Intel
this the same as IOCHK# going active on the ISA bus.
LFRAME# Usage
Start of Cycle
For Memory, I/O, and DMA cycles, the Intel
clock at the beginning of the cycle
ICH will drive LAD[3:0] with the proper START field.
Typical Timing for LFRAME#
Abort Mechanism
When performing an Abort, the Intel
consecutive clocks. On the fourth clock, it will drive LAD[3:0] to ‘1111b’.
The Intel
cases):
•
•
•
•
LFRAME#
LFRAME#
LAD[3:0]
LAD[3:0]
Intel
valid SYNC after four consecutive clocks.
Intel
an invalid SYNC pattern.
A peripheral drives an illegal address when performing bus master cycles.
A peripheral drives an invalid value.
LCLK
LCLK
®
®
®
6300ESB ICH starts a Memory, I/O, or DMA cycle, but no device drives a
6300ESB ICH starts a Memory, I/O, or DMA cycle, and the peripheral drives
6300ESB ICH will perform an abort for the following cases (possible failure
Start
Start
Clock
1
CYCTYPE
Dir & Size
CYCTYPE
Dir & Size
ADDR
(Figure
ADDR
®
Clocks
1 - 8
6300ESB ICH will drive LFRAME# active for four
TAR
®
9) During that clock, the Intel
TAR
Clocks
Syncs causes
6300ESB ICH will assert LFRAME# for one
2
Too many
Sync
timeout
Clocks
Sync
1 - n
Peripheral must
Clocks
Data
stop driving
Intel
2
®
6300ESB ICH will treat
®
6300ESB I/O Controller Hub
TAR
Clocks
2
®
Start
6300ESB
Clock
Chipset will
drive high
1
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