NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 414

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8.8.3.15 DEVTRAP_EN— Device Trap Enable Register
Table 298. DEVTRAP_EN— Device Trap Enable Register
Intel
DS
414
15:1
Bits
Default Value:
9:6
13
12
11
10
I/O Address:
4
5
4
3
®
6300ESB I/O Controller Hub
Lockable:
Note: This register enables the individual trap ranges to generate an SMI# when the
Note: Usage: Legacy only.
Device:
LEG_IO_TRP_EN
AUDIO_TRP_EN
ADLIB_TRP_EN
IDES1_TRP_EN
MIDI_TRP_EN
KBC_TRP_EN
corresponding status bit in the DEVACT_STS register is set. When a range is enabled, I/
O cycles associated with that range will not be forwarded to LPC or IDE.
Reserved
Reserved
Reserved
31
PMBASE +48h
0000h
No
Name
Reserved.
Ad-Lib.
0 = Disable.
1 = Enable.
NOTE: This bit is no longer supported and will not be
KBC (60/64h).
0 = Disable.
1 = Enable.
MIDI.
0 = Disable.
1 = Enable.
NOTE: This bit is no longer supported and will not be
Audio (Sound Blaster “ORed” with MSS).
0 = Disable.
1 = Enable.
NOTE: This bit is no longer supported and will not be
Reserved.
Parallel Port, Serial Port 1, Serial Port 2, Floppy Disk
Controller.
0 = Disable.
1 = Enable.
Reserved.
IDE Secondary Drive 1.
0 = Disable.
1 = Enable.
validated.
validated.
validated.
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write
16-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
R/W
R/W
R/W
R/W
R/W
R/W