NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 515

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

11—Intel
Table 415. Offset CAPLENGTH + 0C - 0Fh: FRINDEX—Frame Index
11.2.2.5 Offset CAPLENGTH + 10 - 13h: CTRLDSSEGMENT—Control
November 2007
Order Number: 300641-004US
31:1
13:0
Bits
Default Value:
4
Note: This 32-bit register corresponds to the most significant address bits [63:32] for all
Device:
®
Offset:
Index/Frame Number
6300ESB ICH
Frame List Current
DWORD. Word and byte writes produce undefined results. This register cannot be
written unless the Host Controller is in the Halted state as indicated by the HCHalted bit
(USB EHCI STS register). A write to this register while the Run/Stop bit is set to a ‘1’
(USB EHCI CMD register) produces undefined results. Writes to this register also effect
the SOF value. See Section 4 of the EHCI Specification for details.
The SOF frame number value for the bus SOF token is derived or alternatively managed
from this register. Please refer to Section 4 of the EHCI Specification for a detailed
explanation of the SOF value management requirements on the host controller. The
value of FRINDEX must be within 125 µs (1 micro-frame) ahead of the SOF token
value. The SOF value may be implemented as an 11-bit shadow register. For this
discussion, this shadow register is 11 bits and is named SOFV. SOFV updates every 8
micro-frames. (1 millisecond). An example implementation to achieve this behavior is
to increment SOFV each time the FRINDEX[2:0] increments from a ’0’ to a ’1’.
Software must use the value of FRINDEX to derive the current micro-frame number,
both for high-speed isochronous scheduling purposes and to provide the get micro-
frame number function required to client drivers. Therefore, the value of FRINDEX and
the value of SOFV must be kept consistent when the chip is reset or software writes to
FRINDEX. Writes to FRINDEX must also write-through FRINDEX[13:3] to
SOFV[10:0]. To keep the update as simple as possible, software should never write a
FRINDEX value where the three least significant bits are 111b or 000b.
Data
Structure Segment Register
EHCI data structures. Since the Intel
Capability field in HCCPARAMS to ‘1’, then this register is used with the link pointers to
construct 64-bit addresses to EHCI control data structures. This register is
concatenated with the link pointer from either the PERIODICLISTBASE,
ASYNCLISTADDR, or any control data structure link field to construct a 64-bit address.
This register allows the host software to locate all control data structures within the
same 4 Gbyte memory segment.
Reserved
29
CAPLENGTH + 0C-0Fh
00000000h
Name
Reserved.
The value in this register increments at the end of each time
frame (e.g., micro-frame).
Bits [12:3] are used for the Frame List current index. This
means that each location of the frame list is accessed eight
times (frames or micro-frames) before moving to the next
index.
®
Description
6300ESB ICH hardwires the 64-bit Addressing
Attribute:
Function:
Size:
7
Read/Write
32-bit
Intel
®
6300ESB I/O Controller Hub
Access
515
DS