NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 747

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

20—Intel
20.1.15 Offset 2Eh - 2Fh: SID—Subsystem ID (SATA–
20.1.16 Offset 34h: CAP—Capabilities Pointer Register
20.1.17 Offset 3Ch: INTR_LN—Interrupt Line Register
November 2007
Order Number: 300641-004US
15:0
Bits
Bits
Bits
Default Value:
Default Value:
Default Value:
7:0
7:0
Table 675. Offset 2Eh - 2Fh: SID—Subsystem ID (SATA–D31:F2)
Table 676. Offset 34h: CAP—Capabilities Pointer Register (SATA–D31:F2)
Table 677. Offset 3Ch: INTR_LN—Interrupt Line Register (SATA–D31:F2)
Lockable:
Device:
Device:
Device:
®
Offset:
Offset:
Offset:
Capability Pointer (CP)
Subsystem ID (SID)
6300ESB ICH
Interrupt Line
D31:F2)
(SATA–D31:F2)
(SATA–D31:F2)
31
2Eh-2Fh
00h
No
Name
31
34h
80h
Name
31
3Ch
00h
Name
The SID register, in combination with the SVID register,
enables the operating system (OS) to distinguish subsystems
from each other. Software (BIOS) sets the value in this
register. After that, the value may be read, but subsequent
writes to this register have no effect. The value written to this
register will also be readable through the corresponding SID
registers for the USB#1, USB#2 and SMBus functions.
This bit indicates that the first capability pointer offset is 80h,
the MSI capability. This value will be 70h if the MAP register
(offset 90h) indicates that the SATA and IDE functions are
combined (values of 100, 101, 110, or 111).
It is to communicate to software the interrupt line that the
interrupt pin is connected to.
Power Well:
Description
Description
Description
Attribute:
Attribute:
Attribute:
Function:
Function:
Function:
Size:
Size:
Size:
2
Read/Write-Once
16-bit
Core
2
Read-Only
8-bit
2
Read/Write
8-bit
Intel
®
6300ESB I/O Controller Hub
Access
Access
Access
R/WO
R/W
RO
747
DS