NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 216

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Intel
DS
216
5.17.8
Table 104. Bits Maintained in Low Power States
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6300ESB I/O Controller Hub
When an Intel
6300ESB ICH halts and immediately issues a hardware interrupt to the system.
Resume Received
This event indicates that the Intel
device on the USB bus during a global suspend. When this interrupt is enabled in the
Interrupt Enable register, a hardware interrupt will be signaled to the system allowing
the USB to be brought out of the suspend state and returned to normal operation.
Intel
The HC monitors certain critical fields during operation to ensure that it does not
process corrupted data structures. These include checking for a valid PID and verifying
that the MaxLength field is less than 1280. When it detects a condition that would
indicate that it is processing corrupted data structures, it immediately halts processing,
sets the HC Process Error bit in the HC Status register and signals a hardware interrupt
to the system.
This interrupt cannot be disabled through the Interrupt Enable register.
Host System Error
The Intel
PCI Target Abort occur. When this error occurs, the Intel
Stop bit in the Command register to prevent further execution of the scheduled TDs.
This interrupt cannot be disabled through the Interrupt Enable register.
USB Power Management
The Host Controller may be put into a suspended state and its power may be removed.
This requires that certain bits of information are retained in the resume power plane of
the Intel
device may be a fax-modem, which will wake up the machine to receive a fax or take a
voice message. The settings of the following bits in I/O space will be maintained when
the Intel
When the Intel
corresponding USB_STS bit in ACPI space. When USB is enabled as a wake/break
event, the system will wake up and an SCI will be generated.
Port Status and
5.17.7.3 Non-Transaction Based Interrupts
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Command
Register
Control
Status
6300ESB ICH Process Error
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6300ESB ICH so that a device on a port may wake the system. Such a
6300ESB ICH enters the S3, S4 or S5 states:
6300ESB ICH sets this bit to 1 when a PCI Parity error, PCI Master Abort, or
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®
6300ESB ICH process error or system error occurs, the Intel
6300ESB ICH detects a resume event on any of its ports, it will set the
10h and 12h
Offset
00h
02h
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Bit
12
6300ESB ICH received a RESUME signal from a
3
2
2
6
8
Enter Global Suspend Mode (EGSM)
Resume Detect
Port Enabled/Disabled
Resume Detect
Low Speed Device Attached
Suspend
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6300ESB ICH clears the Run/
Description
Order Number: 300641-004US
Intel
®
6300ESB ICH—5
November 2007
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