NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 597

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

14—Intel
14.2.5
November 2007
Order Number: 300641-004US
15:0
Bits
Bits
Default Value:
Default Value:
I/O Address:
I/O Address:
2
1
0
Table 521. x_SR—Status Register (Sheet 2 of 2)
Table 522. x_PICB—Position in Current Buffer Register
Lockable:
Lockable:
Note: Software may read the registers at the offsets 08h, 0Ah, and 0Bh by performing a 32-
Device:
Device:
®
DMA Controller Halted
Completion Interrupt
6300ESB ICH
Current Equals Last
Position In Current
Last Valid Buffer
Buffer[15:0]
Valid (CELV)
x_PICB—Position in Current Buffer Register
bit read from address offset 08h. Software may also read this register individually by
doing a single 16-bit read to offset 08h. Reads across dWord boundaries are not
supported.
(LVBCI)
29
MBAR + 06h (MISR),
MBAR + 16h (MOSR)
0001h
No
Name
(DCH)
29
MBAR + 08h (MIPICB),
MBAR + 18h (MOPICB)
0000h
No
Name
0 = Cleared by writing a ‘1’ to this bit position
1 = Set by hardware when last valid buffer has been
0 = Hardware clears when controller exits state (i.e., until a
1 = Current Index is equal to the value in the Last Valid Index
0 = Running.
1 = Halted. This could happen because of the Start/Stop bit
These bits represent the number of samples left to be
processed in the current buffer.
processed. It remains active until cleared by software.
This bit indicates the occurrence of the event signified by
the last valid buffer being processed. Thus, this is an
event status bit that may be cleared by software once
this event has been recognized. This event will cause an
interrupt if the enable bit in the Control Register is set.
The interrupt is cleared when the software clears this bit.
In the case of transmits (PCM out, Modem out), this bit is
set after the last valid buffer has been fetched (not after
transmitting it). In the case of Receives, this bit is set
after the data for the last buffer has been written to
memory.
new value is written to the LVI register).
Register, AND the buffer pointed to by the CIV has been
processed (i.e., after the last valid buffer has been
processed). This bit is very similar to bit 2, except this bit
reflects the state rather than the event. This bit reflects
the state of the controller and remains set until the
controller exits this state.
being cleared and the DMA engines are idle, or it could
happen once the controller has processed the last valid
buffer.
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
5
Read/Write Clear
16-bit
Core
5
Read-Only
16-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
Access
R/WC
RO
RO
RO
597
DS