NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 293

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

7—Intel
7.1.11
Table 157. Offset 19h: SBUS_NUM—Secondary Bus Number Register (HUB-PCI—
7.1.12
Table 158. Offset 1A: SUB_BUS_NUM—Subordinate Bus Number Register (HUB-
7.1.13
November 2007
Order Number: 300641-004US
Bits
Bits
Default Value:
Default Value:
7:0
7:0
®
Device:
Device:
Offset:
Secondary Bus Number
Offset:
6300ESB ICH
Subordinate Bus
Offset 19h: SBUS_NUM—Secondary Bus Number
Register (HUB-PCI—D30:F0)
D30:F0)
Offset 1A: SUB_BUS_NUM—Subordinate Bus
Number Register (HUB-PCI—D30:F0)
PCI—D30:F0)
Offset 1Bh: SMLT—Secondary Master Latency
Timer Register (HUB-PCI—D30:F0)
This Master Latency Timer (MLT) controls the amount of time that the Intel
ICH will continue to burst data as a master on the PCI bus. When the Intel
ICH starts the cycle after being granted the bus, the counter is loaded and starts
counting down from the assertion of FRAME#. When the internal grant to this device is
removed, the expiration of the MLT counter will result in the deassertion of FRAME#.
When the internal grant has not been removed, the Intel
to own the bus.
When the Secondary Master Latency Timer in Device 30 (offset 1Bh) is programmed to
00h (the default value), the North PCI initiator logic operates as though the timer never
expires. Therefore, with this programming, constant consecutive writes from the Hub
Interface to PCI are capable of occupying the PCI bus indefinitely without releasing
FRAME#.
Number
30
19h
00h
Name
30
1A
00h
Name
This field indicates the bus number of PCI.
When this number is equal to the primary bus number (i.e.,
bus #0), the Intel
configuration cycles to this bus number as Type 1
configuration cycles on PCI.
This field specifies the highest PCI bus number below the Hub
Interface to PCI bridge. When a Type 1 configuration cycle
from the Hub Interface does not fall in the Secondary-to-
Subordinate Bus ranges of Device 30, the Intel
ICH will indicate a master abort back to the Hub Interface.
®
6300ESB ICH will run Hub Interface
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0
Read/Write
8-bit
0
Read/Write
8-bit
®
®
6300ESB ICH may continue
Intel
6300ESB
®
6300ESB I/O Controller Hub
®
®
Access
Access
6300ESB
6300ESB
R/W
R/W
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