NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 455

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

9—Intel
9.1.24
9.2
Table 347. Bus Master IDE I/O Registers
November 2007
Order Number: 300641-004US
30:0
Bits
Default Value:
31
Table 346. IDE_CONFIG—IDE I/O Configuration Register (IDE—D31:F1)
®
Device:
Posting Registers (EPPR)
Offset:
6300ESB ICH
Enable Prefetch and
IDE_CONFIG—IDE I/O Configuration Register
(IDE—D31:F1)
Bus Master IDE I/O Registers (D31:F1)
The Bus Master IDE function uses 16 bytes of I/O space, allocated through the BMIBA
register, located in Device 31:Function 1 Configuration space, offset 20h. All bus
master IDE I/O space registers may be accessed as byte, word, or DWORD quantities.
Reading reserved bits returns an indeterminate, inconsistent value, and writes to
reserved bits have no effect, but should not be attempted. The description of the I/O
registers is shown below in
Reserved
54h
00h
Name
Offset
04-07
0C-0F
00
01
02
03
08
09
0A
0B
Mnemonic
BMICS
BMIDS
BMICP
BMISP
BMIDP
BMISS
Until this bit is set, the PPE1 and PPE0 bits in the IDE Timing
Register (bits 6 and 2 of offset 40h for primary, and bits 6 and
2 of offset 42h for secondary) are ignored by the PIO prefetch
and posting hardware. Therefore, even if those bits are set,
PIO posting and prefetching will not occur until this bit is set.
Reserved.
Command Register Primary
Reserved
Status Register Primary
Reserved
Descriptor Table Pointer Primary
Command Register Secondary
Reserved
Status Register Secondary
Reserved
Descriptor Table Pointer Secondary
Table
347.
Description
Register
Attribute:
Function:
Size:
1
R/W
32-bit
Intel
®
6300ESB I/O Controller Hub
xxxxxxxxh
xxxxxxxxh
Default
00h
00h
00h
00h
00h
00h
00h
00h
Access
R/W
R/WC
R/WC
Type
R/W
R/W
R/W
R/W
RO
RO
RO
RO
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DS