NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 65

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

3—Intel
Table 8.
November 2007
Order Number: 300641-004US
®
6300ESB ICH
IDE Interface Signals (Sheet 2 of 2)
NOTES:
SWDMARDY#)
1. The IDE signals are 5V tolerant.
2. The IDE signals have integrated series terminating resistors.
3. All signals may be tri-stated or driven low for mobile swap bays.
PWDMARDY#)
SRDMARDY#)
PRDMARDY#)
PDIOW# /
PDDACK#,
SDIOW# /
(SDWSTB /
PDIOR# /
(PDWSTB /
SDIOR# /
SDDACK#
PIORDY /
SIORDY /
(SDRSTB /
(PDRSTB /
(SDSTOP)
(PDSTOP)
Name
Type
O
O
O
I
Primary and Secondary IDE Device DMA Acknowledge: These
signals directly drive the DAK# signals on the primary and secondary
IDE connectors. Each is asserted by the Intel
indicate to IDE DMA slave devices that a given data transfer cycle
(assertion of DIOR# or DIOW#) is a DMA data transfer cycle. This
signal is used in conjunction with the PCI bus master IDE function and
are not associated with any AT-compatible DMA channel.
Primary and Secondary Disk I/O Read (PIO and Non-Ultra
DMA): This is the command to the IDE device that it may drive data
onto the PDD or SDD lines. Data is latched by the Intel
ICH on the deassertion edge of PDIOR# or SDIOR#. The IDE device is
selected either by the ATA register file chip selects (PDCS1# or
SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the IDE
DMA acknowledge (PDDAK# or SDDAK#).
Primary and Secondary Disk Write Strobe (Ultra DMA Writes to
Disk): This is the data write strobe for writes to disk. When writing to
disk, the Intel
edges of PDWSTB or SDWSTB.
Primary and Secondary Disk DMA Ready (Ultra DMA Reads
from Disk): This is the DMA ready for reads from disk. When reading
from disk, the Intel
SRDMARDY# to pause burst data transfers.
Primary and Secondary Disk I/O Write (PIO and Non-Ultra
DMA): This is the command to the IDE device that it may latch data
from the PDD or SDD lines. Data is latched by the IDE device on the
deassertion edge of PDIOW# or SDIOW#. The IDE device is selected
either by the ATA register file chip selects (PDCS1# or SDCS1#,
PDCS3# or SDCS3#) and the PDA or SDA lines, or the IDE DMA
acknowledge (PDDAK# or SDDAK#).
Primary and Secondary Disk Stop (Ultra DMA): the Intel
6300ESB ICH asserts this signal to terminate a burst.
Primary and Secondary I/O Channel Ready (PIO): This signal
will keep the strobe active (PDIOR# or SDIOR# on reads, PDIOW# or
SDIOW# on writes) longer than the minimum width. It adds wait
states to PIO transfers.
Primary and Secondary Disk Read Strobe (Ultra DMA Reads
from Disk): When reading from disk, the Intel
latches data on rising and falling edges of this signal from the disk.
Primary and Secondary Disk DMA Ready (Ultra DMA Writes to
Disk): When writing to disk, this is deasserted by the disk to pause
burst data transfers.
®
6300ESB ICH drives valid data on rising and falling
®
6300ESB ICH deasserts PRDMARDY# or
Description
Intel
®
®
6300ESB I/O Controller Hub
®
6300ESB ICH to
6300ESB ICH
®
6300ESB
®
DS
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