NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 695

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18—Intel
18.8.11 Error Support
18.8.11.1General
18.8.11.2Special Parity Error Rule for Split Response
18.9
18.9.1
Table 625. Immediate Terminations of Completion Required Cycles to PCI/PCI-X
November 2007
Order Number: 300641-004US
®
6300ESB ICH
As a PCI-X Target, the Intel
Addendum.
When the Intel
Response for a read transaction, it records the error as described in section 5.4.1 of the
PCI/X 1.0 Specification. Furthermore, when the Intel
assert PERR# on the secondary bus and enabled to assert SERR# on the Hub Interface,
it generates NMI/SMI (depending on which is enabled).
Transaction Termination Translation
between Interfaces
Though Intel
software perspective, the Hub Interface is a PCI-X bus and Intel
PCI-X bridge that supports a secondary bus configured as either PCI or PCI-X.
Section 8.7.1.5 of the PCI-X 1.0 Specification modified the behavior of a bridge from
that specified in the PCI to PCI bridge 1.1 spec regarding returning completions on the
primary bus when the secondary bus transaction terminates in either a master abort or
target abort. In general, the PCI-X spec does not honor the Master Abort Mode bit for
cycles requiring completions, and returns to the primary bus the termination that
occurred on the secondary bus without any translation.
The following sections describe the behavior of the Intel
Hub Interface and the PCI/PCI-X under various termination conditions. For specific
information as to why the Intel
a specific termination, see the specific sections on the interface above.
PCI-X
Receiving Immediate Terminations
The behavior described for completion required cycles is independent of the setting of
the Master Abort Mode bit, and is independent of whether the cycle is exclusive
(locked) or not. The Intel
completion that terminates in either Master Abort or Target Abort.
Behavior of Hub Interface Initiated Cycles to PCI/
† The Master Data Parity Error bit is set only when a data parity error is encountered on the PCI/PCI-X bus.
PCI/PCI-X Termination
®
®
6300ESB ICH’s primary bus is the Hub Interface, from a register and
6300ESB ICH calculates a data parity error when a target signals Split
®
®
6300ESB ICH returns all ’1’s on data bytes for a read
6300ESB ICH bridge responds as specified in the PCI-X
®
6300ESB ICH’s PCI, PCI-X, or Hub Interface generates
Hub Interface
Completion
®
6300ESB ICH is enabled to
®
Status Register Bits Set
6300ESB ICH on both the
Intel
®
®
6300ESB I/O Controller Hub
6300ESB ICH is a
695
DS