NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 393

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
8.8.3
Table 283. ACPI and Legacy I/O Register Map
November 2007
Order Number: 300641-004US
®
Note: All reserved bits and registers will always return zero when read and will have no effect
6300ESB ICH
Power Management I/O Registers
Table 283
support. These registers are enabled in the PCI Device 31: Function 0 space
(PM_IO_EN), and may be moved to any I/O location (128-byte aligned). The registers
are defined to be compliant with the ACPI 1.0 specification, and use the same bit
names.
when written.
PMBASE+
4Ch-4Dh
10h-13h
60h-7Fh
00-01h
02-03h
04-07h
08-0Bh
28-2Bh
2C-2Fh
30-33h
34-37h
38-39h
3A-3Bh
Offset
14h
40h
44h
48h
4Eh
shows the registers associated with ACPI and Legacy power management
PM1 Status
PM1 Enable
PM1 Control
PM1 Timer
Processor Control
Level 2 Register
General Purpose Event 0
Status
General Purpose Event 0
Enables
SMI# Control and Enable
SMI Status Register
Alternate GPI SMI Enable
Alternate GPI SMI Status
Device Monitor SMI Status
and Enable
Device Activity Status
Device Trap Enable Register
Bus Address Tracker
Bus Cycle Tracker
Reserved for TCO Registers
Register Name
PM1a_EVT_BLK+2
PM1a_CNT_BLK
PM1a_EVT_BLK
ACPI Pointer
GPE0_BLK+4
PMTMR_BLK
GPE0_BLK
P_BLK+4
P_BLK
Intel
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
Last Cycle
Last Cycle
®
Default
0000h
0000h
0000h
0000h
0000h
0000h
0000h
6300ESB I/O Controller Hub
00h
Attributes
R/WC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
393
DS