NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 652

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18.5
18.5.1
Table 583. Comparison of Rules vs. A PCI – PCI Bridge
18.5.2
Intel
DS
652
®
6300ESB I/O Controller Hub
(normal completion status on the Hub Interface, TRDY# on PCI-X). When more than
one data transfer is requested, the Intel
disconnect operation during the first data phase.
Transaction Ordering
Comparison of Rules vs. a PCI – PCI Bridge
When a PCI segment is in PCI (PCI-X) mode, the Intel
producer-consumer model of a PCI – PCI bridge.
the PCI Specification, Rev 2.2 for PCI, and Section 8.4.4 of the PCI-X Addendum for
PCI-X. The shaded entries represent differences from that table, and an explanation of
the differences:
Other Notes
Ordering relationships are established for the following classes of transactions crossing
the Intel
NOTES:
Delayed (Split) Read
Delayed (Split) Read
1. Subsequent requests only (prefetches). All inbound initial requests are in order.
2. In a bridge, these are allowed to be yes/no.
3. In a bridge, these are allowed to be yes/no. These particular entries are “No” because the
•
•
•
Write Completion
Row Pass Col?
Delayed (Split)
Delayed (Split)
Intel
configuration writes).
Write Request
The Intel
write transaction.
The Intel
the same dWord address.
The Intel
same address into a single write transaction – the PCI Local Bus Specification does
not permit this.
Posted Write
Completion
Request
®
®
6300ESB ICH does not accept inbound write requests that are not posted (I/O writes,
6300ESB ICH:
®
®
®
6300ESB ICH does not combine separate write transactions into a single
6300ESB ICH does not merge bytes on separate write transactions to
6300ESB ICH does not collapse sequential write transactions to the
Posted
Write
No
No
No
No
No
2
Yes
Request
Delayed
(Split)
Read
1
No
Yes
Yes
Yes
®
2
No
6300ESB ICH responds with a target
2
Yes
Table 583
Request
Delayed
(Split)
Write
1
No
Yes
Yes
Yes
®
2
No
6300ESB ICH follows the
3
2
is taken from Appendix E of
Completion
No
No
No
No
Order Number: 300641-004US
Delayed
(Split)
2
3
2
2
Read
Yes
Intel
Yes
Yes
Yes
Yes
®
2
2
2
2
6300ESB ICH—18
November 2007
Completion
No
No
No
Yes
Delayed
(Split)
Write
3
2
2
Yes
3
Yes
Yes
Yes
Yes
2
2
2
2