CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 984

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
986
Register
PORTB
PORTA
DDR
Name
DDRA
DDRB
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1. Always “0” on Port A, B, C, D, E, K, AD0, and AD1.
2. Applicable only on Port P, H, and J.
W
W
W
W
R
R
R
R
IO
0
1
0
1
0
1
0
1
x
x
x
x
x
x
x
DDRA7
DDRB7
All register bits in this module are completely synchronous to internal
clocks during a register read.
Bit 7
PB7
PA7
RDR
x
x
x
x
x
x
x
0
0
1
1
0
0
1
1
= Unimplemented or Reserved
DDRA6
DDRB6
PB6
PA6
Figure 24-2. PIM Register Summary (Sheet 1 of 7)
PE
0
1
1
0
0
1
1
x
x
x
x
x
x
x
x
6
Table 24-3. Pin Configuration Summary
MC9S12XDP512 Data Sheet, Rev. 2.21
PS
0
1
0
1
0
1
0
1
0
1
x
x
x
x
x
DDRA5
DDRB5
1
PB5
PA5
5
IE
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
2
NOTE
DDRA4
DDRB4
PB4
PA4
Input
Input
Input
Input
Input
Input
Input
Output, full drive to 0
Output, full drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
Output, full drive to 0
Output, full drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
4
Function
DDRA3
DDRB3
PB3
PA3
3
DDRA2
DDRB2
PB2
PA2
2
Disabled
Pull Up
Pull Down
Disabled
Disabled
Pull Up
Pull Down
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Pull Device
Freescale Semiconductor
DDRA1
DDRB1
PA1
PB1
1
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
Disabled
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
Interrupt
DDRA0
DDRB0
Bit 0
PB0
PA0