CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 98

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 2 Clocks and Reset Generator (S12CRGV6)

The PLL is used to run the MCU from a different time base than the incoming OSCCLK. For increased

ﬂexibility, OSCCLK can be divided in a range of 1 to 16 to generate the reference frequency. This offers

a ﬁner multiplication granularity. The PLL can multiply this reference clock by a multiple of 2, 4, 6,...

126,128 based on the SYNR register.

The PLL is a frequency generator that operates in either acquisition mode or tracking mode, depending on

the difference between the output frequency and the target frequency. The PLL can change between

acquisition and tracking modes either automatically or manually.

The VCO has a minimum operating frequency, which corresponds to the self clock mode frequency f

supplied by:

Functional Description

Functional Blocks

Phase Locked Loop (PLL)

Although it is possible to set the two dividers to command a very high clock

frequency, do not exceed the speciﬁed bus frequency limit for the MCU.

If (PLLSEL = 1), Bus Clock = PLLCLK / 2

Figure 2-16. PLL Functional Diagram

MC9S12XDP512 Data Sheet, Rev. 2.21

PROGRAMMABLE

PROGRAMMABLE

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Freescale Semiconductor