CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 220

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 6 XGATE (S12XGATEV2)
AND
Operation
RS1 & RS2
RD
Performs a bit wise logical AND of two 16 bit values and stores the result in the destination register RD.
Remark: There is no complement to the BITH and BITL functions. This can be imitated by using R0 as a
destination register. AND R0, RS1, RS2 performs a bit wise test without storing a result.
CCR Effects
Code and CPU Cycles
220
N:
Z:
V:
C:
AND RD, RS1, RS2
AND RD, #IMM16
N
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Refer to ANDH instruction for #IMM16 operations.
0; cleared.
Not affected.
Z
IMM16
V
0
Source Form
—
C
RD
RD (translates to ANDL RD, #IMM16[7:0]; ANDH RD, #IMM16[15:8])
Address
MC9S12XDP512 Data Sheet, Rev. 2.21
Mode
IMM8
IMM8
TRI
Logical AND
0
1
1
0
0
0
0
0
0
1
0
0
0
0
1
Machine Code
RD
RD
RD
RS1
IMM16[15:8]
IMM16[7:0]
RS2
Freescale Semiconductor
AND
0
0
Cycles
P
P
P