CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 841

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

22.3.2.22 Port T Polarity Select Register (PPST)

Read: Anytime.

Write: Anytime.

This register selects whether a pull-down or a pull-up device is connected to the pin.

22.3.2.23 Port S Data Register (PTS)

Read: Anytime.

Write: Anytime.

Port S pins 7–4 are associated with the SPI0. The SPI0 pin configuration is determined by several status

bits in the SPI0 module. Refer to SPI section for details. When not used with the SPI0, these pins can be

used as general purpose I/O.

Port S bits 3–0 are associated with the SCI1 and SCI0. The SCI ports associated with transmit pins 3 and

1 are configured as outputs if the transmitter is enabled. The SCI ports associated with receive pins 2 and

0 are configured as inputs if the receiver is enabled. Refer to SCI section for details. When not used with

the SCI, these pins can be used as general purpose I/O.

If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the

port register, otherwise the buffered pin input state is read.

Freescale Semiconductor

Pull Select Port T

0 A pull-up device is connected to the associated port T pin, if enabled by the associated bit in register PERT

1 A pull-down device is connected to the associated port T pin, if enabled by the associated bit in register PERT

and if the port is used as input.

Figure 22-24. Port T Polarity Select Register (PPST)

Figure 22-25. Port S Data Register (PTS)

Table 22-26. PPST Field Descriptions

MC9S12XDP512 Data Sheet, Rev. 2.21

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)