CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 937

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

23.0.5.31 Port M Input Register (PTIM)

1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the

Read: Anytime.

Write: Never, writes to this register have no effect.

This register always reads back the buffered state of the associated pins. This can also be used to

detect overload or short circuit conditions on output pins.

23.0.5.32 Port M Data Direction Register (DDRM)

Read: Anytime.

Write: Anytime.

This register configures each port M pin as either input or output.

The CAN forces the I/O state to be an output for each port line associated with an enabled output

(TXCAN). also forces the I/O state to be an input for each port line associated with an enabled

input (RXCAN). In those cases the data direction bits will not change.

The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral

module is disabled.

associated pin values.

Data Direction Port M

0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read

on PTM or PTIM registers, when changing the DDRM register.

= Unimplemented or Reserved

Figure 23-34. Port M Data Direction Register (DDRM)

Figure 23-33. Port M Input Register (PTIM)

Table 23-33. DDRM Field Descriptions