CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 354

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CSM9S12XDT512SLK

Manufacturer Part Number
CSM9S12XDT512SLK
Description
KIT STUDENT LEARNING 16BIT
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of CSM9S12XDT512SLK

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
354
Bus Clock
P0
P1
P2
P3
P4
P5
P6
P7
Figure 7-68. Detailed Timer Block Diagram in Queue Mode when PRNT = 1
Pin Logic
Pin Logic
Pin Logic
Pin Logic
Pin Logic
Pin Logic
Pin Logic
Pin Logic
1, 2, 3, ... 256
Prescaler
Timer
EDG0
EDG1
EDG2
EDG3
EDG5
EDG6
8, 12, 16, ... 1024
8, 12, 16, ... 1024
8, 12, 16, ... 1024
8, 12, 16, ... 1024
EDG4
EDG7
SH37
SH04
SH15
SH26
Counter
Counter
Counter
Counter
Delay
Delay
Delay
Delay
MUX
MUX
MUX
MUX
MC9S12XDP512 Data Sheet, Rev. 2.21
16 BIT MAIN TIMER
16-Bit Free-Running
EDG0
EDG1
EDG2
EDG3
Main Timer
TC0 Capture/Compare Reg.
TC1 Capture/Compare Reg.
TC2 Capture/Compare Reg.
TC3 Capture/Compare Reg.
TC4 Capture/Compare Reg.
TC5 Capture/Compare Reg.
TC6 Capture/Compare Reg.
TC7 Capture/Compare Reg.
Bus Clock
TC3H Hold Reg.
TC2H Hold Reg.
TC0H Hold Reg.
TC1H Hold Reg.
Comparator
Comparator
Comparator
Comparator
Comparator
Comparator
Comparator
Comparator
1, 2, 3, ... 256
Prescaler
Modulus
LATQ, BUFEN
(Queue Mode)
Read TC3H
Read TC2H
Read TC1H
Read TC0H
Hold Reg.
Hold Reg.
Hold Reg.
Hold Reg.
PA0H Hold Reg.
PA1H Hold Reg.
PA2H Hold Reg.
PA3H Hold Reg.
PAC0
PAC1
PAC2
PAC3
0
0
0
0
16-Bit Load Register
Freescale Semiconductor
16-Bit Modulus
Down Counter
RESET
RESET
RESET
RESET

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