CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 1266

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Appendix A Electrical Characteristics
If the MCU is woken-up by an interrupt and the fast wake-up feature is enabled (FSTWKP = 1 and
SCME = 1), the system will resume operation in self-clock mode after t
.
fws
A.5.1.5
Pseudo Stop and Wait Recovery
The recovery from pseudo stop and wait are essentially the same since the oscillator was not stopped in
both modes. The controller can be woken up by internal or external interrupts. After t
the CPU starts
wrs
fetching the interrupt vector.
A.5.2
Oscillator
The device features an internal low-power loop controlled Pierce oscillator and a full swing Pierce
oscillator/external clock mode. The selection of loop controlled Pierce oscillator or full swing Pierce
oscillator/external clock depends on the XCLKS signal which is sampled during reset. Before asserting the
oscillator to the internal system clocks the quality of the oscillation is checked for each start from either
power-on, STOP or oscillator fail. t
specifies the maximum time before switching to the internal self
CQOUT
clock mode after POR or STOP if a proper oscillation is not detected. The quality check also determines
the minimum oscillator start-up time t
. The device also features a clock monitor. A clock monitor
UPOSC
failure is asserted if the frequency of the incoming clock signal is below the assert frequency f
CMFA.
MC9S12XDP512 Data Sheet, Rev. 2.21
1268
Freescale Semiconductor