CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 278

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CSM9S12XDT512SLK

Manufacturer Part Number
CSM9S12XDT512SLK
Description
KIT STUDENT LEARNING 16BIT
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of CSM9S12XDT512SLK

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Chapter 6 XGATE (S12XGATEV2)
STB
Operation
RS.L
RS.L
RS.L
RI–1
Stores the low byte of register RD to memory.
CCR Effects
Code and CPU Cycles
1. If the same general purpose register is used as index (RI) and source register (RS), the unmodified content of the source
278
N:
Z:
V:
C:
STB RS, (RB, #OFFS5),
STB RS, (RB, RI)
STB RS, (RB, RI+)
STB RS, (RB, -RI)
N
register is written to the memory: RS.L
Not affected.
Not affected.
Not affected.
Not affected.
Z
RI; RS.L
M[RB, #OFFS5
M[RB, RI
M[RB, RI]; RI+1
V
Source Form
C
M[RB, RI]
RI;
1
Address
MC9S12XDP512 Data Sheet, Rev. 2.21
Mode
IDO5
IDR+
M[RB, RS-1]; RS-1
-IDR
IDR
Store Byte to Memory
0
0
0
0
(Low Byte)
1
1
1
1
0
1
1
1
1
1
1
1
RS
0
0
0
0
Machine Code
RS
RS
RS
RS
RB
RB
RB
RB
RI
RI
RI
Freescale Semiconductor
OFFS5
STB
0
0
1
0
1
0
Cycles
Pw
Pw
Pw
Pw

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