CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 861

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.3.2.48 Port H Data Direction Register (DDRH)
Read: Anytime.
Write: Anytime.
This register configures each port H pin as either input or output.
If the associated SCI channel or routed SPI module is enabled this register has no effect on the pins.
The SCI forces the I/O state to be an output for each port line associated with an enabled output (TXD5,
TXD4). It also forces the I/O state to be an input for each port line associated with an enabled input (RXD5,
RXD4). In those cases the data direction bits will not change.
If a SPI module is enabled, the SPI determines the pin direction. Refer to SPI section for details.
The DDRH bits revert to controlling the I/O direction of a pin when the associated peripheral modules are
disabled.
Freescale Semiconductor
DDRH[7:0]
Reset
Field
7–0
W
R
DDRH7
Data Direction Port H
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
0
7
on PTH or PTIH registers, when changing the DDRH register.
DDRH6
0
6
Figure 22-50. Port H Data Direction Register (DDRH)
Table 22-45. DDRH Field Descriptions
DDRH5
MC9S12XDP512 Data Sheet, Rev. 2.21
0
5
DDRH4
0
4
Description
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
DDRH3
0
3
DDRH2
0
2
DDRH1
0
1
DDRH0
0
0
863