CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 345

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.3.2.27
Read: Anytime
Write: Anytime
All bits reset to zero.
Freescale Semiconductor
PTMPS7
Table 7-34. Precision Timer Modulus Counter Prescaler Select Examples when PRNT = 1 (continued)
Reset
PBOVI
PBEN
Field
0
0
0
0
0
1
6
1
W
R
Pulse Accumulator B System Enable — PBEN is independent from TEN. With timer disabled, the pulse
accumulator can still function unless pulse accumulator is disabled.
0 16-bit pulse accumulator system disabled. 8-bit PAC1 and PAC0 can be enabled when their related enable bits
1 Pulse accumulator B system enabled. The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form
Pulse Accumulator B Overflow Interrupt Enable
0 Interrupt inhibited
1 Interrupt requested if PBOVF is set
16-Bit Pulse Accumulator B Control Register (PBCTL)
PTMPS6
0
0
7
in ICPAR are set.
the PACB 16-bit pulse accumulator B. When PACB is enabled, the PACN1 and PACN0 registers contents are
respectively the high and low byte of the PACB.
PA1EN and PA0EN control bits in ICPAR have no effect.
The PACB shares the input pin with IC0.
0
0
0
0
1
1
Figure 7-49. 16-Bit Pulse Accumulator B Control Register (PBCTL)
= Unimplemented or Reserved
PBEN
PTMPS5
0
6
0
0
0
1
1
1
Table 7-35. PBCTL Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
PTMPS4
0
0
5
0
0
1
1
1
1
PTMPS3
0
0
4
0
1
1
1
1
1
Description
PTMPS2
Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
0
0
3
1
1
1
1
1
1
PTMPS1
0
0
2
1
1
1
1
1
1
PTMPS0
PBOVI
0
1
1
1
1
1
1
1
Prescaler
Division
Rate
128
256
16
32
64
0
0
0
8
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