CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 350

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
Read: Anytime
Write: Has no effect.
All bits reset to zero.
These registers are used to latch the value of the input capture registers TC0–TC3. The corresponding
IOSx bits in TIOS should be cleared (see
7.4
This section provides a complete functional description of the ECT block, detailing the operation of the
design from the end user perspective in a number of subsections.
350
Reset
Reset
W
W
R
R
Functional Description
TC15
TC7
15
0
0
7
Figure 7-63. Timer Input Capture Holding Register 3 High (TC3H)
= Unimplemented or Reserved
= Unimplemented or Reserved
Figure 7-64. Timer Input Capture Holding Register 3 Low (TC3H)
TC14
TC6
14
0
0
6
MC9S12XDP512 Data Sheet, Rev. 2.21
TC13
TC5
13
0
0
5
Section 7.4.1.1, “IC
TC12
TC4
12
0
0
4
TC11
TC3
11
Channels”).
0
0
3
TC10
TC2
10
0
0
2
Freescale Semiconductor
TC9
TC1
0
0
9
1
TC8
TC0
0
0
8
0