CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 560

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 14 Voltage Regulator (S12VREG3V3V5)

The VREGAPICL register allows the conﬁguration of the VREG_3V3 autonomous periodical interrupt

Autonomous Periodical Interrupt Clock Select Bit — Selects the clock source for the API. Writable only if

APIFE = 0; APICLK cannot be changed if APIFE is set by the same write operation.

0 Autonomous periodical interrupt clock used as source.

1 Bus clock used as source.

Autonomous Periodical Interrupt Feature Enable Bit — Enables the API feature and starts the API timer

0 Autonomous periodical interrupt is disabled.

1 Autonomous periodical interrupt is enabled and timer starts running.

Autonomous Periodical Interrupt Enable Bit

0 API interrupt request is disabled.

1 API interrupt will be requested whenever APIF is set.

Autonomous Periodical Interrupt Flag — APIF is set to 1 when the in the API conﬁgured time has elapsed.

This ﬂag can only be cleared by writing a 1 to it. Clearing of the ﬂag has precedence over setting.

Writing a 0 has no effect. If enabled (APIE = 1), APIF causes an interrupt request.

0 API timeout has not yet occurred.

1 API timeout has occurred.

Autonomous Periodical Interrupt Control Register (VREGAPICL)

Figure 14-4. Autonomous Periodical Interrupt Control Register (VREGAPICL)

= Unimplemented or Reserved

Table 14-4. VREGAPICL Field Descriptions

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor