CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 212

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 6 XGATE (S12XGATEV2)

For load and store instructions (RS, RI) provides a variable offset in a register.

[RS, RI+] provides a variable offset in a register, which is incremented after accessing the memory. In case

of a byte access the index register will be incremented by one. In case of a word access it will be

incremented by two.

[RS, -RI] provides a variable offset in a register, which is decremented before accessing the memory. In

case of a byte access the index register will be decremented by one. In case of a word access it will be

decremented by two.

Any register can be loaded either with an immediate or from the address space using indexed addressing

The same set of modes is available for the store instructions

Instruction Summary and Usage

Index Register plus Register Offset (IDR)

Index Register plus Register Offset with Post-increment (IDR+)

Index Register plus Register Offset with Pre-decrement (–IDR)

Load & Store Instructions

RD,(RB, RI+)

RS,(RB, RI+)

MC9S12XDP512 Data Sheet, Rev. 2.21

; loads a byte from R1+R2 into R4

; stores R4 as a word to R1+R2

; loads a byte from R1+R2 into R4, R2+=1

; stores R4 as a word to R1+R2, R2+=2

; R2 -=1, loads a byte from R1+R2 into R4

; R2 -=2, stores R4 as a word to R1+R2

; loads an immediate 8 bit value to the lower byte of RD

; loads data using RB+RI as effective address

; followed by an increment of RI depending on

; the size of the operation

; stores data using RB+RI as effective address

; followed by an increment of RI depending on

; the size of the operation.

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