CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 182

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
5.4.2.2
The input channel pins can be multiplexed between analog and digital data. As analog inputs, they are
multiplexed and sampled to supply signals to the A/D converter. As digital inputs, they supply external
input data that can be accessed through the digital port register PORTAD (input-only).
The analog/digital multiplex operation is performed in the input pads. The input pad is always connected
to the analog inputs of the ATD. The input pad signal is buffered to the digital port registers. This buffer
can be turned on or off with the ATDDIEN register. This is important so that the buffer does not draw
excess current when analog potentials are presented at its input.
5.4.2.3
The ATD can be configured for lower MCU power consumption in 3 different ways:
Note that the reset value for the ADPU bit is zero. Therefore, when this module is reset, it is reset into the
power down state.
5.5
At reset the ATD is in a power down state. The reset state of each individual bit is listed within the Register
Description section (see
and their bit-field.
5.6
The interrupt requested by the ATD is listed in
vector address and priority.
See register descriptions for further details.
182
1. Stop mode: This halts A/D conversion. Exit from stop mode will resume A/D conversion, but due
2. Wait mode with AWAI = 1: This halts A/D conversion. Exit from wait mode will resume A/D
3. Writing ADPU = 0 (Note that all ATD registers remain accessible.): This aborts any A/D
to the recovery time the result of this conversion should be ignored.
conversion, but due to the recovery time the result of this conversion should be ignored.
conversion in progress.
Resets
Interrupts
General Purpose Digital Input Port Operation
Low Power Modes
Section 5.3, “Memory Map and Register
Sequence complete
Interrupt Source
interrupt
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 5-24. ATD Interrupt Vectors
Table
Mask
CCR
I bit
5-24. Refer to the device overview chapter for related
ASCIE in ATDCTL2
Local Enable
Definition”), which details the registers
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