CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 952

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
23.0.5.57 Port J Reduced Drive Register (RDRJ)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each port J output pin as either full or reduced. If the port is
used as input this bit is ignored.
23.0.5.58 Port J Pull Device Enable Register (PERJ)
Read: Anytime.
Write: Anytime.
954
DDRJ[7:4]
DDRJ[2:0]
RDRJ[7:4]
RDRJ[2:0]
Reset
Reset
Field
Field
7–0
7–0
W
W
R
R
RDRJ7
PERJ7
Data Direction Port J
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
Reduced Drive Port J
0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
0
1
7
7
on PTJ or PTIJ registers, when changing the DDRJ register.
= Unimplemented or Reserved
= Unimplemented or Reserved
RDRJ6
PERJ6
Figure 23-60. Port J Pull Device Enable Register (PERJ)
0
1
6
6
Figure 23-59. Port J Reduced Drive Register (RDRJ)
Table 23-52. DDRJ Field Descriptions
Table 23-53. RDRJ Field Descriptions
RDRJ5
PERJ5
MC9S12XDP512 Data Sheet, Rev. 2.21
0
1
5
5
RDRJ4
PERJ4
0
1
4
4
Description
Description
0
0
0
0
3
3
RDRJ2
PERJ2
0
1
2
2
RDRJ1
Freescale Semiconductor
PERJ1
0
1
1
1
RDRJ0
PERJ0
0
1
0
0