CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 190

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 6 XGATE (S12XGATEV2)
190
XGSWEIFM
XGFACTM
XGDBG
XGFRZ
XGIEM
Field
XGE
11
9
8
7
6
5
XGFACT Mask — This bit controls the write access to the XGFACT bit. The XGFACT bit can only be set or
cleared if a "1" is written to the XGFACTM bit in the same register access.
Read:
Write:
0 Disable write access to the XGFACT in the same bus cycle
1 Enable write access to the XGFACT in the same bus cycle
XGSWEIF Mask — This bit controls the write access to the XGSWEIF bit. The XGSWEIF bit can only be cleared
if a "1" is written to the XGSWEIFM bit in the same register access.
Read:
Write:
0 Disable write access to the XGSWEIF in the same bus cycle
1 Enable write access to the XGSWEIF in the same bus cycle
XGIE Mask — This bit controls the write access to the XGIE bit. The XGIE bit can only be set or cleared if a "1"
is written to the XGIEM bit in the same register access.
Read:
Write:
0 Disable write access to the XGIE in the same bus cycle
1 Enable write access to the XGIE in the same bus cycle
XGATE Module Enable — This bit enables the XGATE module. If the XGATE module is disabled, pending
XGATE requests will be ignored. The thread that is executed by the RISC core while the XGE bit is cleared will
continue to run.
Read:
0 XGATE module is disabled
1 XGATE module is enabled
Write:
0 Disable XGATE module
1 Enable XGATE module
Halt XGATE in Freeze Mode — The XGFRZ bit controls the XGATE operation in Freeze Mode (BDM active).
Read:
0 RISC core operates normally in Freeze (BDM active)
1 RISC core stops in Freeze Mode (BDM active)
Write:
0 Don’t stop RISC core in Freeze Mode (BDM active)
1 Stop RISC core in Freeze Mode (BDM active)
XGATE Debug Mode — This bit indicates that the XGATE is in Debug Mode (see
Debug Mode can be entered by Software Breakpoints (BRK instruction), Tagged or Forced Breakpoints (see
S12X_DBG Section), or by writing a "1" to this bit.
Read:
0 RISC core is not in Debug Mode
1 RISC core is in Debug Mode
Write:
0 Leave Debug Mode
1 Enter Debug Mode
Note: Freeze Mode and Software Error Interrupts have no effect on the XGDBG bit.
This bit will always read "0".
This bit will always read "0".
This bit will always read "0".
Table 6-1. XGMCTL Field Descriptions (Sheet 2 of 3)
MC9S12XDP512 Data Sheet, Rev. 2.21
Description
Section 6.6, “Debug
Freescale Semiconductor
Mode”).