CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 113

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.5
This section describes how to reset the CRG, and how the CRG itself controls the reset of the MCU. It
explains all special reset requirements. Since the reset generator for the MCU is part of the CRG, this
section also describes all automatic actions that occur during or as a result of individual reset conditions.
The reset values of registers and signals are provided in
Definition”. All reset sources are listed in
addresses and priorities.
2.5.1
The reset sequence is initiated by any of the following events:
Upon detection of any reset event, an internal circuit drives the RESET pin low for 128 SYSCLK cycles
(see
the internal reset circuit of the CRG cannot sequence out of current reset condition without a running
SYSCLK. The number of 128 SYSCLK cycles might be increased by n = 3 to 6 additional SYSCLK cycles
depending on the internal synchronization latency. After 128 + n SYSCLK cycles the RESET pin is
released. The reset generator of the CRG waits for additional 64 SYSCLK cycles and then samples the
RESET pin to determine the originating source.
Freescale Semiconductor
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Figure
Low level is detected at the RESET pin (external reset)
Power on is detected
Low voltage is detected
Illegal Address Reset is detected (see S12XMMC Block Guide for details)
COP watchdog times out
Clock monitor failure is detected and self-clock mode was disabled (SCME=0)
Resets
2-25). Since entry into reset is asynchronous, it does not require a running SYSCLK. However,
Description of Reset Operation
COP Watchdog Reset
Illegal Address Reset
Clock Monitor Reset
Low Voltage Reset
Power on Reset
External Reset
Reset Source
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 2-14. Reset Summary
Table
2-14. Refer to MCU specification for related vector
Table 2-15
Section 2.3, “Memory Map and Register
PLLCTL (CME = 1, SCME = 0)
COPCTL (CR[2:0] nonzero)
shows which vector will be fetched.
Local Enable
Chapter 2 Clocks and Reset Generator (S12CRGV6)
None
None
None
None
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