CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 1203

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CSM9S12XDT512SLK

Manufacturer Part Number
CSM9S12XDT512SLK
Description
KIT STUDENT LEARNING 16BIT
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of CSM9S12XDT512SLK

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
29.3.2.7
The FCMD register is the Flash command register.
All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not
writable.
29.3.2.8
The FCTL register is the Flash control register.
All bits in the FCTL register are readable but are not writable.
The FCTL NV bits are loaded from the Flash nonvolatile byte located at global address 0x7F_FF0E during
the reset sequence, indicated by F in
Freescale Semiconductor
CMDB[6:0]
Reset
Reset
Field
6:0
W
W
R
R
Flash Command — Valid Flash commands are shown in
listed in
Flash Command Register (FCMD)
Flash Control Register (FCTL)
0
1
0
0
7
7
Table 29-16
= Unimplemented or Reserved
= Unimplemented or Reserved
NV6
1
F
6
6
Figure 29-12. Flash Command Register (FCMD)
sets the ACCERR flag in the FSTAT register.
Figure 29-13. Flash Control Register (FCTL)
Table 29-16. Valid Flash Command List
Table 29-15. FCMD Field Descriptions
CMDB[6:0]
MC9S12XDP512 Data Sheet, Rev. 2.21
0x05
0x06
0x20
0x40
0x41
0x47
NV5
Figure
F
0
5
5
29-13.
NV4
0
F
4
4
Sector Erase Abort
Description
NVM Command
Data Compress
Word Program
Sector Erase
Erase Verify
Mass Erase
CMDB
Table
NV3
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1)
F
0
3
3
29-16. Writing any command other than those
NV2
0
F
2
2
NV1
F
0
1
1
NV0
0
F
0
0
1205

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