CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 217

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADD
Operation
RS1 + RS2
RD IMM16
Performs a 16 bit addition and stores the result in the destination register RD.
CCR Effects
Code and CPU Cycles
Freescale Semiconductor
N:
Z:
V:
C:
ADD RD, RS1, RS2
ADD RD, #IMM16
N
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS1[15] & RS2[15] & RD[15]
Refer to ADDH instruction for #IMM16 operations.
Set if there is a carry from bit 15 of the result; cleared otherwise.
RS1[15] & RS2[15] | RS1[15] & RD[15]
Refer to ADDH instruction for #IMM16 operations.
Z
V
Source Form
C
RD
RD (translates to ADDL RD, #IMM16[7:0]; ADDH RD, #[15:8])
new
TRI
IMM8
IMM8
| RS1[15] & RS2[15] & RD[15]
Address
MC9S12XDP512 Data Sheet, Rev. 2.21
Mode
new
Add without Carry
| RS2[15] & RD[15]
0
1
1
0
1
1
0
1
1
1
0
0
1
0
1
new
new
Machine Code
RD
RD
RD
RS1
IMM16[15:8]
IMM16[7:0]
Chapter 6 XGATE (S12XGATEV2)
RS2
ADD
1
0
Cycles
P
P
P
217