CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 177

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

This read-only register contains the conversion complete ﬂags.

Read: Anytime

Write: Anytime, no effect

Freescale Semiconductor

Conversion Complete Flag x (x = 7, 6, 5, 4, 3, 2, 1, 0) — A conversion complete ﬂag is set at the end of each

conversion in a conversion sequence. The ﬂags are associated with the conversion position in a sequence (and

also the result register number). Therefore, CCF0 is set when the ﬁrst conversion in a sequence is complete and

the result is available in result register ATDDR0; CCF1 is set when the second conversion in a sequence is

complete and the result is available in ATDDR1, and so forth. A ﬂag CCFx (x = 7, 6, 5, 4, 3, 2,1, 70) is cleared

when one of the following occurs:

In case of a concurrent set and clear on CCFx: The clearing by method A) will overwrite the set. The clearing by

methods B) or C) will be overwritten by the set.

0 Conversion number x not completed

1 Conversion number x has completed, result ready in ATDDRx

ATD Status Register 1 (ATDSTAT1)

A) Write to ATDCTL5 (a new conversion sequence is started)

B) If AFFC=0 and read of ATDSTAT1 followed by read of result register ATDDRx

C) If AFFC=1 and read of result register ATDDRx

= Unimplemented or Reserved

Figure 5-12. ATD Status Register 1 (ATDSTAT1)

Table 5-20. ATDSTAT1 Field Descriptions

MC9S12XDP512 Data Sheet, Rev. 2.21

Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)