CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 692

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 19 S12X Debug (S12XDBGV2) Module
19.1.2
19.1.3
The DBG module can be used in all MCU functional modes.
During BDM hardware accesses and when the BDM module is active, CPU monitoring is disabled. Thus
breakpoints, comparators and bus tracing mapped to the CPU are disabled but accessing the DBG registers,
including comparator registers, is still possible. While in active BDM or during hardware BDM accesses,
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Four comparators (A, B, C, and D):
— Comparators A and C compare the full address and the full 16-bit data bus
— Comparators A and C feature a data bus mask register
— Comparators B and D compare the full address bus only
— Each comparator can be configured to monitor either CPU or XGATE busses
— Each comparator features control of R/W and byte/word access cycles
— Comparisons can be used as triggers for the state sequencer
Three comparator modes:
— Simple address/data comparator match mode
— Inside address range mode, Addmin Address Addmax
— Outside address range match mode, Address Addmin or Address Addmax
Two types of triggers:
— Tagged: triggers just before a specific instruction begins execution
— Force: triggers on the first instruction boundary after a match occurs.
Three types of breakpoints:
— CPU breakpoint entering BDM on breakpoint (BDM)
— CPU breakpoint executing SWI on breakpoint (SWI)
— XGATE breakpoint
Three trigger modes independent of comparators:
— External instruction tagging (associated with CPU instructions only)
— XGATE S/W breakpoint request
— TRIG bit immediate software trigger
Three trace modes:
— Normal: change of flow (COF) bus information is stored (see
— Loop1: same as normal but inhibits consecutive duplicate source address entries
— Detail: address and data for all cycles except free cycles and opcode fetches are stored
4-stage state sequencer for trace buffer control:
— Tracing session trigger linked to final state of state sequencer
— Begin, end, and mid alignment of tracing to trigger
Mode”) for change of flow definition.
Features
Modes of Operation
MC9S12XDP512 Data Sheet, Rev. 2.21
Section 19.4.5.2.1, “Normal
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